Non-volatile memory cells are well known in the art. One prior art non-volatile split gate memory cell 10, which contains five terminals, is shown in FIG. 1. Memory cell 10 comprises semiconductor substrate 12 of a first conductivity type, such as P type. Substrate 12 has a surface on which there is formed a first region 14 (also known as the source line SL) of a second conductivity type, such as N type. A second region 16 (also known as the drain line) also of N type is formed on the surface of substrate 12. Between the first region 14 and the second region 16 is channel region 18. Bit line BL 20 is connected to the second region 16. Word line WL 22 is positioned above a first portion of the channel region 18 and is insulated therefrom. Word line 22 has little or no overlap with the second region 16. Floating gate FG 24 is over another portion of channel region 18. Floating gate 24 is insulated therefrom, and is adjacent to word line 22. Floating gate 24 is also adjacent to the first region 14. Floating gate 24 may overlap the first region 14 to provide coupling from the first region 14 into floating gate 24. Coupling gate CG (also known as control gate) 26 is over floating gate 24 and is insulated therefrom. Erase gate EG 28 is over the first region 14 and is adjacent to floating gate 24 and coupling gate 26 and is insulated therefrom. The top corner of floating gate 24 may point toward the inside corner of the T-shaped erase gate 28 to enhance erase efficiency. Erase gate 28 is also insulated from the first region 14. Memory cell 10 is more particularly described in U.S. Pat. No. 7,868,375, whose disclosure is incorporated herein by reference in its entirety.
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. Memory cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on erase gate 28 with other terminals equal to zero volts. Electrons tunnel from floating gate 24 into erase gate 28 causing floating gate 24 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state.
Memory cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on coupling gate 26, a high voltage on source line 14, a medium voltage on erase gate 28, and a programming current on bit line 20. A portion of electrons flowing across the gap between word line 22 and floating gate 24 acquire enough energy to inject into floating gate 24 causing the floating gate 24 to be negatively charged, turning off the cell 10 in a read condition. The resulting cell programmed state is known as ‘0’ state.
Memory cell 10 is read in a Current Sensing Mode as following: A bias voltage is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias or zero voltage is applied on erase gate 28, and a ground is applied on source line 14. There exists a cell current flowing from bit line 20 to source line 14 for an erased state and there is insignificant or zero cell current flow from the bit line 20 to the source line 14 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Current Sensing Mode, in which bit line 20 is grounded and a bias voltage is applied on source line 24. In this mode the current reverses the direction from source line 14 to bitline 20.
Memory cell 10 alternatively can be read in a Voltage Sensing Mode as following: A bias current (to ground) is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias voltage is applied on erase gate 28, and a bias voltage is applied on source line 14. There exists a cell output voltage (significantly >0V) on bit line 20 for an erased state and there is insignificant or close to zero output voltage on bit line 20 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Voltage Sensing Mode, in which bit line 20 is biased at a bias voltage and a bias current (to ground) is applied on source line 14. In this mode, memory cell 10 output voltage is on the source line 14 instead of on the bit line 20.
In the prior art, various combinations of positive or zero voltages were applied to word line 22, coupling gate 26, and floating gate 24 to perform read, program, and erase operations
In response to the read, erase or program command, the logic circuit 270 (in FIG. 2) causes the various voltages to be supplied in a timely and least disturb manner to the various portions of both the selected memory cell 10 and the unselected memory cells 10.
For the selected and unselected memory cell 10, the voltage and current applied are as follows. As used hereinafter, the following abbreviations are used: source line or first region 14 (SL), bit line 20 (BL), word line 22 (WL), and coupling gate 26 (CG).
TABLE NO. 1Operation of Flash Memory Cell 10 Using Positive Voltages for Read, Erase,and ProgramWL-BL-CG-unselCG-EG-WLunselBLunselCGsame sectorunselEGunselRead1.0-2 V  0 V0.6-2 V  0 V- 0-2.6 V 0-2.6 V0-2.6 V0-2.6 V0-2.6 VFLTErase0 V0 V0 V0 V   0 V0-2.6 V0-2.6 V11.5-12 V 0-2.6 VProgram1 V0 V 1 uAVinh10-11 V0-2.6 V0-2.6 V4.5-5 V0-2.6 VSLSL-unselRead0 V0 V-FLTErase0 V0 V   Program4.5-5 V  0-1 V/FLT 
In a recent application by the applicant—U.S. patent application Ser. No. 14/602,262, filed on Jan. 21, 2015, which is incorporated by reference—the applicant disclosed an invention whereby negative voltages could be applied to word line 22 and/or coupling gate 26 during read, program, and/or erase operations. In this embodiment, the voltage and current applied to the selected and unselected memory cell 10, are as follows.
TABLE NO. 2Operation of Flash Memory Cell 10 Using Negative Voltages for Read and/orProgramWL-BL-CG-unselCG-EG-WLunselBLunselCGsame sectorunselEGunselRead1.0-2 V  −0.5 V/0 V0.6-2 V  0 V- 0-2.6 V 0-2.6 V0-2.6 V0-2.6 V0-2.6 VFLTErase0 V0 V0 V0 V   0 V0-2.6 V0-2.6 V11.5-12 V 0-2.6 VProgram1 V−0.5 V/0 V 1 uAVinh10-11 V0-2.6 V0-2.6 V4.5-5 V0-2.6 VSLSL-unselRead0 V0 V-FLTErase0 V0 V   Program4.5-5 V  0-1 V/FLT 
In another embodiment of U.S. patent application Ser. No. 14/602,262, negative voltages can be applied to word line 22 when memory cell 10 is unselected during read, erase, and program operations, and negative voltages can be applied to coupling gate 26 during an erase operation, such that the following voltages are applied:
TABLE NO. 3Operation of Flash Memory Cell 10 Using Negative Voltages for EraseWL-BL-CG-unselCG-EG-WLunselBLunselCGsame sectorunselEGunselRead1.0-2 V  −0.5 V/0 V0.6-2 V  0-0-2.6 V     0-2.6 V0-2.6 V0-2.6 V  0-2.6 VFLTErase0 V−0.5 V/0 V0 V0-−(5-9) V      0-2.6 V0-2.6 V8-9 V0-2.6 VFLTProgram1 V−0.5 V/0 V 1 uAVinh8-9 VCGINTH (4-6 V)0-2.6 V8-9 V0-2.6 VSLSL-unselRead0 V0-FLTErase0 V0 V   Program4.5-5 V  0-1 V/FLT 
The CGINH signal listed above is an inhibit signal that is applied to the coupling gate 26 of an unselected cell that shares an erase gate 28 with a selected cell.
FIG. 2 depicts an embodiment of another prior art flash memory cell 210. As with prior art flash memory cell 10, flash memory cell 210 comprises substrate 12, first region (source line) 14, second region 16, channel region 18, bit line 20, word line 22, floating gate 24, and erase gate 28. Unlike prior art flash memory cell 10, flash memory cell 210 does not contain a coupling gate or control gate and only contains four terminals—bit line 20, word line 22, erase gate 28, and source line 14. This significantly reduces the complexity of the circuitry, such as decoder circuitry, required to operate an array of flash memory cells.
The erase operation (erasing through erase gate) and read operation are similar to that of the FIG. 1 except there is no control gate bias. The programming operation also is done without the control gate bias, hence the program voltage on the source line is higher to compensate for lack of control gate bias.
Table No. 4 depicts typical voltage ranges that can be applied to the four terminals for performing read, erase, and program operations:
TABLE NO. 4Operation of Flash Memory Cell 210WL-BL-WLunselBLunselEGEG-unselSLSL-unselRead0.7-2.2 V−0.5 V/0 V 0.6-2 V  0 V/FLT0-2.6 V0-2.6 V0 V   0 V/FLT/VBErase−0.5 V/0 V−.5 V/0 V0 V0 V   11.5 V0-2.6 V0 V0 V  Program  1-1.5 V−.5 V/0 V1-3 μA Vinh  4.5 V0-2.6 V7-9 V  0-1 V/FLT(~1.8 V)
FIG. 3 depicts an embodiment of another prior art flash memory cell 310. As with prior art flash memory cell 10, flash memory cell 310 comprises substrate 12, first region (source line) 14, second region 16, channel region 18, bit line 20, and floating gate 24, and erase gate 28. Unlike prior art flash memory cell 10, flash memory cell 310 does not contain a coupling gate or control gate or an erase gate. In addition, word line 322 replaces word line 22 and has a different physical shape than word line 22, as depicted.
One exemplary operation for erase and program of prior art non-volatile memory cell 310 is as follows. The cell 310 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the word line 322 and zero volts to the bit line and source line. Electrons tunnel from the floating gate 24 into the word line 322 causing the floating gate 24 to be positively charged, turning on the cell 310 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 310 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the source line 14, a small voltage on the word line 322, and a programming current on the bit line 320. A portion of electrons flowing across the gap between the word line 322 and the floating gate 24 acquire enough energy to inject into the floating gate 24 causing the floating gate 24 to be negatively charged, turning off the cell 310 in read condition. The resulting cell programmed state is known as ‘0’ state.
Exemplary voltages that can be used for the read, program, erase, and standby operations in memory cell 310 are shown below in Table 5:
TABLE NO. 5Operation of Flash Memory Cell 310OperationWLBLSLReadVwlrdVblrd0 VProgramVwlpIprog/Vinh (unsel)VslpEraseVwler0 V0 VStandby0 V0 V0 VVwlrd ~2-3 VVblrd ~0.8-2 VVwlp ~1-2 VVwler ~11-13 VVslp ~9-10 VIprog ~1-3uaVinh ~2 V
Also known in the prior art are various techniques for performing address fault detection in a memory system. Address faults sometimes occur due to imperfections in materials or due to radiation, such as solar flares, which can cause a “1” bit to flip to a “0” bit and vice-versa within an address. The result of an address fault is that a decoder might receive an intended address for an operation, but due to a fault occurring, a bit in the decoder will be altered, and the decoder might activate the word line corresponding to a different address, which will cause the wrong row in a memory array to be accessed. Another possible result is that the fault will result in the decoder activating the word line corresponding to the intended address and a word line corresponding to another address different than the intended address. If not detected or corrected, an address fault will cause an erroneous read or write/program operation to occur.
FIG. 4 depicts prior art memory system 400. Prior art memory system 400 comprises row decoder 410 and array 420. Row decoder 410 receives address X, which here is an address or portion of an address corresponding to a selected row in array 420. Row decoder 410 decodes address X and selects a word line corresponding to that selected row. In this simplified example, four words lines are shown—WL0 (corresponding to address 0000), WL1 (corresponding to address 0001), WL2 (corresponding to address 0010), and WL3 (corresponding to address 0011). The selected word line will activate a row of memory cells within array 420. Thus for example, if address 0010 is received, row decoder 410 will activate WL2 (corresponding to address 0010).
FIG. 5 depicts prior art memory system 400 as in FIG. 4. However, in this situation, an address fault has occurred. Row decoder 410 receives address 0010, but this time, instead of activating WL2 (corresponding to address 0010), row decoder 410 instead activates WL3 (corresponding to address 0011) due to a fault that occurred in row decoder 410. If this fault is undetected or uncorrected, an erroneous read or program operation occurs.
FIG. 6 depicts prior art memory system 400 as in FIGS. 4 and 5. However, in this situation, a different type of address fault has occurred than in FIG. 4. Row decoder 410 receives address 0010, but this time, instead of activating only WL2 (corresponding to address 0010), row decoder 410 instead activates WL2 and WL3 (corresponding to address 0011) due to a fault that occurred in row decoder 410. If this fault is undetected or uncorrected, an erroneous read or program operation will occur.
FIG. 7 depicts prior art memory system 700. Memory system 700 comprises row decoder 410 and array 420 as in the memory systems of previous figures. However, the word lines, such as WL0, WL1, WL2, and WL3, also are coupled to ROM (read-only memory) 710. ROM 710 performs a validation function. Each word line is coupled to a row of cells in ROM 710. When a particular word line is activated, the corresponding row of cells in ROM 710 is activated. By design, each word line corresponds to one row in ROM 710, and each row in ROM 710 stores a different value in its cells. In this example, each row in ROM 710 stores a value that is identical to the address corresponding to the word line tied to that row. Thus, WL0 corresponds to address 0000, and the value stored in the row in ROM 710 attached to WL0 also is 0000.
In FIG. 8, memory system 700 is again depicted. Row decoder 410 receives address 0010, but due to a fault condition, WL3 (corresponding to address 0011) is selected instead of WL2 (corresponding to address 0010). This will cause the wrong row of memory cells to be selected in array 420. Because WL3 is activated, the row in ROM 710 corresponding to WL3 also is activated, and ROM 710 outputs value 0011 stored in that row. Comparator 450 compares the address received by row decoder 410 (i.e., 0010) with the output of ROM 710 (i.e., 0011) and determines the values do not match. Comparator 450 can then output a value (such as “0”) that is understood to mean that a match was not found, which will indicate that an address fault has occurred.
Although prior art memory system 700 is able to detect address faults where the wrong word line is activated, prior art memory system 700 is unable to detect a fault in at least some situations where multiple rows are selected instead of just one row. In FIG. 9, memory system 700 again is depicted. In this example, an address fault occurs where the word line for the intended row (i.e., WL2 for address 0010) is activated and another word line (i.e., WL3 for address 0011) is activated. WL2 and WL3 will both be activated, and the contents for both rows in ROM 710 will be output. Logically, ROM 710 is designed such that when two rows are activated, the output will be an “OR” of the two rows. Thus, the stored values of 0010 and 0011 will cause the output to be 0011. Comparator 450 will compare the address received by row decoder 410 (i.e., 0010) and the output of ROM 710 (i.e., 0011). In this instance, a fault will be detected. However, if instead the intended address was 0011, and the fault was such that the word lines corresponding to 0010 and 0011 were again activated, then the output of ROM 710 would be 0011 (which is the same as the address received by row decoder 410), and the comparator would not detect a fault. Thus, it can be appreciated that memory system 700 is not always effective at identifying address faults of this type where two rows are selected instead of one row.
What is needed is an improved address fault detection system that can identify two types of address faults in a memory system, namely, a first situation where the wrong word line is asserted and a second situation where the right word line is asserted but a second line also is asserted.